A Novel approach to design secure and reliable SRAM from power analysis attack using power equalizer circuit

Power analysis side channel attacks are very prominent among attackers to extract secret data temporarily stored in SRAM. This paper presents a novel method in which a power equalizer circuit is used in 6T cell to design secure and reliable memory in all three operations. Monte-Carlo simulations of 1000 samples has been performed to obtain data prediction probability which is 0.03%, 1.36% and 1.88% during read, write and hold operations respectively for proposed cell.