Design and Optimization of Speed and Power in FinFET Based Binary and Ternary CAM Cells and 4x4 CAM Arrays Using MTCMOS and GDI Techniques

Content Addressable Memories (CAMs) are primarily used in routers and packet forwarding. The biggest problems in CAM design are the parallel comparison of Match Lines (MLs), latency, and power usage. This paper discusses the following techniques for reducing the latency and power: a binary 4T CAM cell, a 4x4 CAM array, novel 8T and 4T TCAM cells, a 4x4 TCAM array, Multi-Threshold CMOS (MTCMOS), and Gate Diffusion Input (GDI). The proposed binary MTCMOS CAM cell reduces the power dissipation by 31% and the delay by 11%, while the GDI CAM cell reduces the delay by 94.4%. The power consumed by the 8T-TCAM cell in the proposed TCAM designs is 754.5 nW, and the delay is 1015.4 ps. The 4T-TCAM cell reduces the power consumption by 37.65% and the delay by 18% compared to the 8T-TCAM cell. To further reduce the power and delay, the MTCMOS technique was applied to the 4T-TCAM cell. This resulted in a 32.5% reduction in power and a 13.09% reduction in delay, using Cadence 18nm FinFETs.