Design of Content-Addressable Memory for Big Data Applications Using 18nm FINFET Technology

This study provides an innovative method to construct a 4x4 Binary Content Addressable Memory (CAM) with the integration of Split Rail Charge Recovery Logic (SRCL), an Adiabatic logic. The proposed design leverages the benefits of Split Charge Recovery logic to achieve enhanced energy efficiency and reduced power dissipation during computational operations. The 18nm technology node is employed to capitalize on the advancements in semiconductor manufacturing, enabling compact and efficient integration of the CAM cells. The core of the design features a 4x4 matrix CAM structure, providing the capability to store and retrieve binary data based on content rather than traditional memory addresses for big data application. By applying Split Rail Charge Recovery Logic (SCRL) and making several architectural modifications, the 4x4 SCRL Binary CAM shows considerable gains in power efficiency, with an average dynamic power decrease of 39% and an average static power fall of 20%. The integration of Split Rail Charge Recovery Logic (SCRL) ensures charge management during logic transitions, contributing to lower overall power consumption and improved performance.