In this paper, a nested g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> − C loops operational amplifier has been implemented, using cascade gain stages, Miller compensation capacitors and feedforward amplifying paths. Special care is given to thoroughly analyze the mathematical background of this compensation technique. The implemented circuit is designed and post-layout simulated in TSMC 90 nm CMOS technology node using the Cadence IC Suite. According to the simulation results the implemented architecture improves the stability performance of the circuit, achieving 89.45 ◦ phase margin along with 101.3 dB DC gain.
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Koniavitis et al. (2024) studied this question.
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