Triple-Node-Upset Recoverable Radiation-Hardened by Design Latch

CMOS technology evolution enhances integrated circuits (ICs) performance characteristics at the cost of their increased susceptibility to radiation and thus to the occurrence of single-event upsets (SEUs) that may lead to soft errors generation. SEUs may affect multiple nodes in a circuit (multiple node upsets - MNUs). Fortunately, these disturbances do not cause permanent damage to the circuits. Various techniques have been proposed to deal with SEUs that concurrently affect one, two or three nodes. In this paper, we propose the design of a latch that offers tolerance up to the level of triple-node upsets (TNUs). This is achieved by using redundancy in the hardware which provides the ability to store a logic value in multiple nodes within the latch as well as by using multiple feedback paths which allow it to recover its correct state in the event of an SEU. Compared to other techniques dealing with the same problem, our proposed method provides faster recovery time (higher than 16.87%) after an SEU, and at the same time reduced power consumption and higher speed performance.