A Triple‐Node‐Upset Self‐Recovery Latch Features Low Soft Error Rate for Aerospace Applications

In this paper, the principle of N‐polarity design is verified by 3D technology computer‐aided design (TCAD) tool at the device level. Then, based on the N‐polarity design, a basic module named N‐polarity interlocked module (N‐PIM) is proposed. By employing dual modular redundancy (DMR), a low‐cost triple‐node‐upset self‐recovery (LSTNUR) latch with a low soft error rate (SER) is proposed. Due to employ the N‐polarity design, the proposed latch exhibits a few numbers of sensitive nodes and achieves a low SER with a wide supply voltage, which suggest that the proposed LSTNUR latch exhibits better soft error tolerability. Compared with state‐of‐the‐art TNU‐hardened latches, including TTLL, LCTNUT, FATNU, IHTRL, DOCTRL, and TRLW, the proposed LSTNUR latch achieves a decrease of power consumption by 53.02%, D‐Q delay by 23.72%, C‐Q delay by 36.35%, and power‐delay‐area product by 77.00%, respectively. Furthermore, process, voltage, and temperature (PVT) variations have a little effect on the power consumption and D‐Q delay of proposed LSTNUR latch, which suggests the proposed latch exhibits a superior reliability. Therefore, the LSTNUR latch can be used in radiation environment.