TCAD Simulations of Reconfigurable Field-Effect Transistor With Embedded-Fin-Contact to Improve On-Current

Reconfigurable field effect transistors (RFETs) hold promise for next-generation VLSI technology. This work presents a Fin-type RFET structure with embedded-Fin-contact designed (EFC-RFET) to overcome the limitation of low ON-state saturation current ( <tex-math notation="LaTeX">I_on</tex-math> ). The results show that <tex-math notation="LaTeX">I_on</tex-math> of the proposed EFC-RFET under both n-type and p-type programs improves about two orders of magnitude, compared to its conventional counterpart. The unique side tunneling, induced by the embedded Fin within the silicide source and drain contributes to the saturation current of the proposed EFC-RFET. Geometry parameters, including the length of the Fin embedded in the source and the drain ( <tex-math notation="LaTeX">LEF</tex-math> ), Fin width ( <tex-math notation="LaTeX">WFin</tex-math> ), and Fin height ( <tex-math notation="LaTeX">HFin</tex-math> ), are investigated to ascertain their impacts on dc, ac, and RF characteristics. Furthermore, the propagation delay of a basic combination logic circuit is found to reduce by about two orders of magnitude. The underlying physical mechanism is discussed in detail. This work paves a novel path for the design of high-performance RFET devices.