Novel Reconfigurable Transistor With Extended Source/Drain Beyond 3 nm Technology Node

In this work, a novel stacked nanosheet reconfigurable field effect transistor with extended source/drain (ESD-NSRFET) is proposed to improve ON-current ( <tex-math notation="LaTeX">I ON </tex-math> ), where an additional extended source/drain is intersected between the vertically stacked nanosheets. Compared to the conventional nanosheet RFET (NSRFET), <tex-math notation="LaTeX">I ON </tex-math> of proposed ESD-NSRFET with 4 nm extended source is demonstrated to improve by <tex-math notation="LaTeX">176× </tex-math> and <tex-math notation="LaTeX">80× </tex-math> for n-type and p-type program, respectively. Geometry parameters like extended source/drain length <tex-math notation="LaTeX">L ESD </tex-math> , nanosheet width <tex-math notation="LaTeX">W NS </tex-math> , and nanosheet thickness <tex-math notation="LaTeX">T NS </tex-math> are investigated in point of <tex-math notation="LaTeX">I ON </tex-math> . Considering the trade-off between increased tunneling strength and degraded parasitic source resistance, <tex-math notation="LaTeX">L ESD </tex-math> in ESD-NSRFET should be carefully designed to obtain optimal current. The underlying physical mechanism is also discussed in detail.