Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (N W ), nanosheet thickness (N T ), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO 2 ) spacer produces a higher switching ratio ( <?CDATA 7.28× 10¹¹?> 7.28 × 10 11 ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by <?CDATA 1.11× 10¹?> 1.11 × 10 1 and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by <?CDATA 2.34× 10⁻²?> 2.34 × 10 − 2 A and improves the switching ratio by <?CDATA 2.90× 10¹.?> 2.90 × 10 1 . An increase in the source doping level from <?CDATA 1× 10²⁰?> 1 × 10 20 to <?CDATA 5× 10²⁰?> 5 × 10 20 cm −3 results in a <?CDATA 1.07× 10²?> 1.07 × 10 2 decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is <?CDATA 1× 10¹⁷?> 1 × 10 17 cm −3 . Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.