Electrical Stress on the CMOS Inverters Made by Junctionless Gate-All-Around Transistors

Junctionless gate-all-around (JLGAA) transistors hold promise for improved performance and scalability, thanks to their junctionless (JL) design. However, challenges such as high gate leakage persist. The interfacial gate oxide defects in JLGAA MOSFETs may differ from those in conventional MOSFETs due to their high doping and unique channel fabrication. This study investigates their reliability, finding that under medium reverse drain and gate bias, not only JLGAA pMOSFETs but also nMOSFETs may experience either a decrease in threshold voltage ( <tex-math notation="LaTeX">Vₜ)</tex-math> or a <tex-math notation="LaTeX">Vₜ</tex-math> turnaround effect over time. All devices exhibit a deteriorated subthreshold swing (S.S.) following normal or reverse bias stress. Device simulation suggests that positive bias induces medium electrical stress at the dielectric of pMOSFETs compared with negative bias, particularly at the interfacial SiO <tex-math notation="LaTeX">₂</tex-math> .