Impact of Metal-Gate-Induced Stress on Device- and Circuit-Level Performance of GAAFET CMOS Inverters

Gate-all-around field-effect transistors (GAAFETs) are promising candidates for next-generation CMOS technology because they satisfy both low-power and high-performance requirements. However, their nanoscale geometry makes them highly sensitive to intrinsic stress generated during gate formation, which can affect both device characteristics and circuit operation. In this study, the effects of metal-gate-induced intrinsic stress on GAAFET-based CMOS inverters were systematically investigated with respect to nanosheet width (WNS). Sentaurus TCAD simulations were performed to analyze stress distributions, threshold voltages, saturation currents, and effective currents in NMOS and PMOS devices. In addition, circuit characteristics, including voltage transfer curves, noise margins, fan-out-of-three delay times, overshoot/undershoot voltages, switching energy, and energy-delay product, were evaluated. The results show that NMOS and PMOS devices exhibit opposite current variations under identical stress conditions, which may lead to current imbalance and operational asymmetry in CMOS circuits. Furthermore, WNS was identified as an important parameter governing stress sensitivity. Smaller WNS values increased variations in device characteristics, whereas larger WNS values showed greater delay sensitivity to stress. These findings demonstrate that WNS is a critical design factor for improving performance balance and reliability in stress-aware GAAFET circuit design.