Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance

With the increasing speed and more stringent Bit Error Rate (BER) requirements of serial wireline links, FPGA-based SerDes (serializer/deserializer) simulation systems have gained widespread usage. As a fundamental component for BER simulation, there is a growing demand for Gaussian random number (GRN) generators that offer enhanced statistical accuracy, improved efficiency, and greater scalability. In this paper, we introduce a novel design methodology for GRN generators tailored for SerDes simulation systems. Unlike conventional approaches, this methodology treats GRNs as discrete values, is optimizable for specific GRN variances, supports pre-determined output ranges, and offers complete reconfigurability with respect to variance. A theoretical output range of <tex-math notation="LaTeX">± 14σ</tex-math> is exemplified. Synthesis results and statistical tests demonstrated that generators designed using the proposed method are statistically accurate while consuming low resources and providing complete reconfigurability.