ASIC SoC Design for Edge Computing Agriculture Application

This paper introduces an ASIC implementation tailored for agriculture applications, leveraging RISC-V for digital processing and sensor interfacing circuits. The design focuses on early plant disease detection and yield improvement. Three sensors for temperature, humidity, and crop wetness are integrated for edge computing, processing data closer to the source. The design includes both analog and digital ASICs, with analog circuits designed based on sensor specifications. Multi-technology node designs and stacking of two ASICs are explored for shorter and denser connections. The RISC core has an area of 50927 μ m², critical path delay of 361 ps, and power consumption of 420 pW after placement and routing. The analog ASIC, covering signal processing components, has a combined routed length of 23358 pm and a total area of 2.366 mm2, tested with AMS verification methodology using Cadence CAD tools.