ASIC Chip Design For Healthcare System

This paper presents an Application-Specific Integrated Circuit (ASIC) implementation suitable for healthcare applications that employ RISC-V as a digital processing unit and sensor interfacing circuits. Systems on Chip (SoC) are used as monitoring tools for well-being or precautionary. Healthcare system with ultra-low-power System on Chip (SoC) architecture specifically for wearable healthcare systems, in order to reduce the power consumption of the processor, designing an ASIC that handles signal processing and provides computation. The design consists of two sensors for collecting the force/pressure and ECG signal data. The design of analog circuits is done using the specifications obtained with these sensors. The RTL-based design of a processor is implemented using Verilog HDL. Logic Equivalence is verified using Xilinx ISE. Physical realizations of the design are obtained using RTL to GDSII design flow. The analog design consists of a Unity Gain Buffer, sample and holds circuit, and flash-type ADC. We have tested ASICs with AMS verification methodology using Cadence CAD tools. Analog ASIC has area of 4,40,000 µm 2 , power dissipation 4.4 mW and the Digital ASIC operating frequency of the overall system is observed at 2.85 GHz, and the area of the digital core is 18088.380 µm 2 . The total Power dissipation of the core is 368 µW.