Ultra-Deep via Etching of Silicon Oxide for High-Voltage Capacitive Isolators

High-voltage capacitive isolators typically use SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as the dielectric layer, and the required thickness of silicon oxide is generally large. However, as the size of the pattern in the integrated circuit decreases, the thickness of the intermetallic dielectric layer decreases accordingly, resulting in the cumulative thickness of all the intermetallic dielectric layers having difficulty in meeting the requirement. In order to achieve the high-voltage withstand target, we added an extra dielectric layer above the top metal layer, but this method increased the difficulty of silicon oxide etching. In this study, we investigated the effects of etching conditions, such as mask material, mask thickness, and etching process parameters on ultra-deep via etching of silicon oxide, and obtained a single maximum etching depth of 8 um for silicon oxide.