New Generation Test Framework Solution for Complicated Multi-Die Chip on ATE

With the development of ChipLet technique in the semiconductor industry, more and more chips are consist of multi dies and each die is designed by many different kinds of analog IP or complicated high-speed interface PHY, which has been facing much more serious challenges (such as the efficiency of complicated pattern iteration, the strict control of bench correlation condition, the promotion of test coverage, etc). Under this background, this paper will provide a new generation test solution for the above challenges of complicated Multi-Die chip and a common program framework on ATE (Auto Test Equipment) has been implement to support the solution.