Improved Performance of PMOS by Optimizing the Epitaxial Morphology

Since the emergence of the fully depleted silicon on insulator (FDSOI) structure, it has exhibited a wide range of potential applications due to its notable advantages in terms of exceptional radiation resistance and low power consumption. However, owing to the distinctive nature of the FDSOI structure, numerous challenges are encountered during its manufacturing process. We found that the epitaxial morphology at the source and drain of a PMOS device can have an impact on the electrical performance of the device. In this study, we optimized the SiGe epitaxial morphology in PMOS source and drain regions within FDSOI structures by adjusting process parameters such as temperature, effectively resolving issues related to abnormal epitaxial growth. Consequently, significant enhancements were achieved in terms of Ion-Ioff performance while ensuring minimal drain induced barrier lowering (DIBL).