Breakdown Voltage Improvement of LDMOS by CESL Optimization in High-Voltage 90 NM BCD Technology

The Bipolar-CMOS-DMOS (BCD) technology has been widely used in smart-power application (5–100 V). However, the plasma damage of back end of line (BEOL) restricts its breakdown voltage (BV) of LDMOS in BCD and limits its further application in high voltage field (>100 V). In this paper, we optimize the contact etch stop layer (CESL) to improve the off-B- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vds</tex> of LDMOS in 90 nm BCD technology. Replacing CESL from SiN to SiON can decrease the trapping electrons on the silicon surface and relieve the limitation of off-B <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vds</tex> improvement. The optimized NLDMOS exhibits an off-B- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vds</tex> of 130 V, which is 28% higher than the old baseline. These results enable a low cost and simple process for power management applications.