A 5.27nW/kHz Low Power Relaxation Oscillator with Current Consumption Reduction Technique

Aiming at the problem that high power consumption in traditional relaxation oscillators, this paper presents a design of a low power relaxation oscillator. This relaxation oscillator achieves power consumption reduction by incorporating a logic-controlled switch on the voltage comparator, reducing the current supply during non-operational periods. Additionally, digital trimming is introduced to correct frequency deviations caused by process variations. Based on a 180-nm CMOS process, and the layout design and post-simulation are conducted using Cadence. The layout area is 0.034 mm². Simulation results show that operating at 1.2 V, achieves an oscillation frequency of 25 kHz with a power consumption of 5.27 nW/kHz. With the temperature range from -60 to 110°C, the temperature coefficient of the oscillation frequency is 235.3 ppm/°C. With the supply voltage range from 1 to 3 V, the linear sensitivity of the oscillation frequency is 2%/V.