Computation-in-Memory Based Boolean Circuit Design Using Tunnel FET Based 8T SRAM

Modern computing has rapidly progressed with ultra-compact devices using the von Neumann architecture, which separates memory from processing. Yet, Computation in Memory (CIM) is rectifying these separations for efficiency's sake. Leading the forefront, Tunnel Field-Effect Transistors (TFETs) are set to transform computer memory, boasting faster speeds with lower power consumption. Due to impressive IONIIOFF ratios, swift transitions, and negligible leakage - credited to exceptional subthreshold swings ( 40m V /decade) - TFETs are ideal for economical power usage. This analysis utilizes Cadence for SRAM libraries with n-type and p-type TFETs, comparing them to FinFETs under 22nm technology and a 1.2V supply. Results indicate TFETs outperform in lowering dynamic power and leakage against conventional CMOS technology. Notably, transitioning from CNTFET to TFET, here achieved a 30 to 50 percent reduction in both Power Delay Product and Energy Delay Product, highlighting TFET's ascendant role in In-Memory Computing.