Design of Carbon Nanotube Field Effect Transistor Based Random Access Memory

Complementary Metal Oxide Semiconductor (CMOS) technology has been ruling the semiconductor since last five decades. Scaling of CMOS is well proven. CMOS technology may face the scaling problems if it goes beyond the limit. Therefore, there has to be alternate technology to the CMOS technology to achieve designs with low power and less delay. Carbon Nanotube Field Effect Transistor (CNTFET) technology is useful for the implementation of low power and less delay designs. Memory is an integral part of any design. In this paper, CNTFET based SRAM is implemented and compared with CMOS technology. Both are implemented in Cadence Virtuoso using 45 nm technology node. The CNFET cell libraries provided by Stanford University are incorporated in Cadence Virtuoso. This paper presents the complete process of integrating CNFET libraries in Cadence Virtuoso. Further, CMOS and CNFET based SRAM using 45 nm technology are implemented. The performance parameter power and delay of both the technologies are compared.