Silicon Carbide Dmosfet Design Adaptation for LOW Interface Trap Density

The channel mobility of a SiC-based double implanted power MOSFET (DMOSFET) is relatively small due to scattering by the interface trap charges. With recent advancements in fabrication technologies, the trap density at the SiC/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface is successfully lowered (but not the oxide fixed charge density). The long-standing problem of low channel mobility has been thought to be solved, but our simulations here - with experimentally reported mobility numbers - show that there is a confounding effect from a reduction in threshold voltage (Vₜₕ) due to the decreased interface trap density. To resolve this, we present a device design with restored V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> , and a thicker - ergo, more reliable - oxide, with the lower interface trap density. In the process, we find that with the lowered interface trap density (and unchanged oxide fixed charge density) there is a trade-off required between the on-resistance (Ro n) and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> .