Growth mechanisms and characteristics of near-interface traps in SiC/SiO2 interfaces for next generation power devices: A short review

Silicon carbide (SiC) has emerged as a leading wide-bandgap semiconductor for high-voltage and high-temperature power electronics; however, the performance of SiC metal–oxide–semiconductor (MOS) devices remain limited by the electrical quality of the SiC/SiO 2 interface. This review discusses the oxidation mechanisms governing SiO₂ formation on SiC, with particular emphasis on conventional thermal oxidation and plasma-assisted oxidation, and examines their influence on interface trap density (D it ), near-interface traps (NITs), channel mobility, and dielectric reliability. The discussion focuses on the Deal–Grove oxidation model and the Massoud empirical relation, which are the principal frameworks used to interpret oxidation kinetics in the representative studies reviewed, together with theoretical approaches describing charge trapping and carrier transport. Recent experimental studies are critically examined to compare oxidation routes, interface characterization techniques, and reliability behavior. Representative reports demonstrate that optimized plasma-assisted oxidation and interface engineering can reduce D it to the low 10 10 –10 11 cm −2 eV −1 range, while optimized low-pressure thermal oxidation has reduced NIT density from 88.3 × 10 11 –10.2 × 10 11 cm⁻² and improved dielectric breakdown strength from 7.8 to 10.6 MV/cm. This review furthers with the advantages and limitations of thermal oxidation, plasma-assisted oxidation, and NO/N 2 O passivation, along with highlighting the importance of integrating oxidation kinetics, interface chemistry, NIT characterization, and dielectric reliability for the development of stable, high-mobility SiC MOS interfaces for the next-generation power electronics.