Demonstration of Low Interface Trap Density (~3×10¹¹eV⁻¹cm⁻²) SiC/SiO₂ MOS Capacitor with Excellent Performance Using H₂+NO POA Treatment for SiC Power Devices

In this work, we report on the engineering of the SiC/SiO 2 MOS interface using H 2 treatments along with NO POA to improve the interface characteristics and device reliability. Significantly low D it of 3×10 11 eV -1 cm -2 , stable threshold voltage, and long gate oxide lifetime > 10 5 s have been achieved by H 2 annealing before NO POA of thermal SiO 2 . Through device electrical characterization and material analysis, we show that the performance enhancement is due to the reduction of interface defects and trapped charges in the SiO 2 surface layer after the POA treatment, which in turn, significantly suppresses the threshold voltage instability.