Backside power delivery (PowerVia) represents an inflection point in interconnect evolution. With the impending transition of PowerVia from development to high-volume-manufacturing (HVM) at Intel, the rest of the silicon industry is racing to deploy the same. This paper describes approaches to implementing backside power delivery & shows transistor performance data from Intel on both FinFET & RibbonFET. Impact of backside power on design, EDA, manufacturing, reliability and other "perceived" challenges is also discussed. Silicon results from an X-86 Intel E-Core test-chip validating PowerVia benefits are detailed.
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Shamanna et al. (2024) studied this question.
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