Breaking Barriers: Unleashing the Potential of High-Efficiency 500 W 4-to-1 IBC through Innovative 3D-PCB Design and Power Inlay Semiconductor Technology

In the rapidly evolving landscape of artificial intelligence (AI) applications, the demand for high-power density and high-efficiency solutions has become increasingly paramount [1]. Specifically, in the context of 48V AI applications, the role of DC-DC converters has proven crucial in delivering the required power with optimal efficiency [2]. In this paper, the zero-voltage-switching converter (ZSC) [3], [4] is adopted with the multi-die Power Inlay semiconductor package in order to develop a high-efficiency 4–to–1 intermediate bus converter architecture. The proposed module offers a maximum efficiency of η <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> ≈ 98.1%, and is capable of delivering up to 505W output power with efficiency of η <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">maxPower</inf> = 95.89% in a form factor of 50mm × 10mm operating a frequency of 1.1MHz. Using the power inlay package, enables the usage of conventional PCB process in order to create chip-embedding based modules. The embedding of pre-packaged power MOSFETs (Power Inlays) in the module's PCB unlocks extra degrees of freedom in PCB and system optimizations and allows novel 3D-PCB designs implementing vertical current flow to reduce layout associated parasitic resistances. The design of a module using multi-die power inlays is presented in this paper and assessed with finite-element-analysis (FEA) simulation, circuit-level simulation, and 500W – 1.1MHz, 4 − to − 1 experimental prototype including measurement results.