The precision Nyquist ADC space (>16b) is typically limited to throughput levels up to 15MS/s, the resolution of the converters >5MS/s being limited to 18b resolution [1–8]. Two-stage SAR ADCs dominate this space, but as the throughput increases the input and reference become difficult to drive, suffer from settling errors, and tend to degrade the FOM. This paper presents a two-stage SAR ADC with dynamically interleaved first stage and easy-to-drive input and reference signals, achieving 20b linearity and 9.3nV/rtHz noise spectral density, implemented in a 40nm CMOS process.
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Bodnar et al. (2024) studied this question.
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