An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input

High-speed ADCs are key blocks for ADC-based serial links [1]. The SAR ADC is credited for its high energy efficiency while speedup is a challenge. One limiting factor to the SAR ADC speed is metastability. Traditional solutions have to lengthen the time or speed up the comparator for metastability tolerance, leading to a trade-off between speed and power consumption. A better way to solve metastability is by monitoring the comparison time of the comparator <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(tcomp)</tex> and correcting codes. Prior research [2] extracts an additional bit of code from metastability by detecting <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tcomp</tex> . However, since the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tcomp</tex> is sensitive to the input common-mode voltage (VCM), VCM-based switching is a must to ensure the accuracy of the obtained 1-bit code, which limits the speed of [2] to 700MS/s with 6b resolution. This work acquires two-bit codes from metastability and further accelerates the conversion. An on-chip self-tuning delay is adopted to ensure the accuracy of the extra 2 bits against PVT changes. This work also employs a bi-directional switching logic to speed up conversion and a proper comparator structure to minimize the impact of VCM changes. Thanks to the technique mentioned above, this work achieves 47. 2dB SNDR at 1GSs} with a Nyquist input. The 8b SAR ADC consumes 4. 15mW and 0.0032mm 2 including on-chip self-tuning delay, leading to a Walden FoM of 22.23fJ/conv.-step.