High-performance computing for AI and supercomputing applications are pushing the power and performance envelopes exponentially in highly volume constrained environments. This market segment is driving up the complexity of systems on package (SoP) and, power delivery in conjunction with heat removal are emerging as dominant bottlenecks. These demand reticle sized dies, and the process yields often dictate disaggregated approaches where the SoP consists of numerous stacked dies, each with varied functionality (computing, high bandwidth memory, IO) that span across many different process nodes [1]. The power delivery to these die complexes is particularly challenging as the lateral edges of the SoCs are reserved for data interfaces. This segues into the need for a VR chiplet due to the following reasons.
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Jain et al. (2024) studied this question.
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