High-Performance On-Chip Low-Dropout Regulators for HBM and SoC Power Integrity: Architectures, Metrics, and Design Perspectives

The rapid growth of artificial-intelligence (AI) and high-performance computing workloads has reshaped the power-delivery requirements of high-bandwidth memory (HBM), neural processing units (NPUs), and advanced systems-on-chip (SoCs). These platforms draw large currents that vary rapidly at aggressively scaled supply voltages, so their on-chip regulators must combine high current density, nanosecond-scale settling with minimal droop, wideband power-supply rejection (PSR), and stable capacitor-less operation, while also mitigating issues such as power supply-induced jitter (PSIJ) in high-speed clock and data paths. On-chip low-dropout (LDO) regulators have become the key building block at the point of load, and a wide range of architectures have emerged to meet these demands. This paper reviews on-chip LDOs for HBM and SoC power integrity. We translate application-level power-integrity requirements, including PSIJ, into circuit specifications; organize the design space into fast-transient, wideband high-PSR, high-current and distributed, and capacitor-less and digital/hybrid architectures; benchmark representative state-of-the-art designs using both conventional and application-relevant metrics such as data rate, jitter, and eye margin; and distill the resulting technology trends.