A Review on Distributed Voltage Regulators for High-Performance Integrated Circuits

Conventional power distribution networks (PDNs), in which individual voltage regulators power the entire integrated circuit (IC), are inef-fective for high-power, large-area ICs. In high-performance systems-on-chip (SoCs) and micro-processors (in particular those designed for AI applications), shrinking technology nodes are leading to higher current densities, which im-pose thermal constraints and limit the portion of the chip that can be simultaneously pow-ered (“dark silicon”). PDNs with point-of-load regulation offer a promising alternative. The distributed nature of their design inher-ently relaxes thermal constraints while minimiz-ing high-current routing overhead (IR drops), thereby improving the PDN efficiency. In this work, the concept of on-chip distributed voltage regulation is introduced. Previously reported distributed voltage regulator designs are re-viewed, emphasizing their major achievements and limitations. Then, the challenges that hin-der a more ubiquitous adoption of such designs, namely stability (analysis) and unbalanced load sharing, are discussed. Existing solutions ad-dressing these challenges are also presented. Fi-nally, a comparative analysis of the performance of these regulators is presented, and insights into the future direction of distributed voltage regu-lation are offered.