14.9 A Monolithic 10.5W/mm²600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS

With the industry moving to a disaggregated approach to constructing modern complex SoC designs, a large variety of digital, IO and PHY IP blocks are needed to be integrated on multiple advanced CMOS processes. Each IP on any given process node desires an optimal voltage to meet its performance and power efficiency goals. Delivering the aggregated sum of unique rails across all IPs, across die-stacks from the platform is extremely challenging, given the shrinking form factors of modern electronic systems. Furthermore, to maximize battery life, these IP blocks are actively lowering voltages, and are utilizing workload or activity-based supply voltages, like traditional DVFS, necessitating the need for localized voltage regulators (VR).