November 21, 2025ElectronicsOpen Access

A 4–5 GHz Sub-Sampling PLL with TDC-Free Digital Coarse Loop

View Full Paper

Ask AI

Bookmark

RMS jitter reaches 177 fs, showcasing enhanced performance in phase-locked loop technology.
Frequency-domain analysis demonstrates effective fractional-N operation without a time-to-digital converter.
The design incorporates a delta–sigma modulator for improved frequency alignment across narrow locking ranges.
This novel approach highlights significant area efficiency and power reduction in PLL implementations.

Authors

JJJaeyun Jang YKYoungsik Kim SKShinwoong Kim

Discussion

No takes yet. Share an insight, caveat, or question.

Implication

Innovative PLL design reduces RMS jitter to 177 fs using a time-to-digital converter to enhance frequency control with an efficient area of 0.146 mm².

Cite This Study

Jang et al. (2025) studied this question.

synapsesocial.com/papers/6924e3f2c0ce034ddc34f150 https://doi.org/10.3390/electronics14234558

View Full Paper

Ask AI

Bookmark

Implication

Innovative PLL design reduces RMS jitter to 177 fs using a time-to-digital converter to enhance frequency control with an efficient area of 0.146 mm².

A 4–5 GHz Sub-Sampling PLL with TDC-Free Digital Coarse Loop

Key Points

Discussion

Implication

Cite This Study

A 4–5 GHz Sub-Sampling PLL with TDC-Free Digital Coarse Loop

Key Points

Discussion

Implication

Cite This Study

Also Consider

Also Consider