A 40-nm 3.9mW, 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface

Brain-machine interface (BMI) technology enables the human brain to communicate directly with machines. This work presents a neural signal processor for real-time BMI, supporting translation from user's speech attempt to sentences. By employing speech attempt detection, the energy consumption is reduced by 46% and the number of channels for speech attempt detection can be decreased from 128 to 16. The proposed weight encoding, which leverages both sparse encoding and mixed-precision arithmetic, reduces the off-chip memory size of the neural network by 80%. Computation reordering decreases the processing latency by 55%. For the partial sum caching technique, the number of neural network operations is reduced by 25%. The processing element (PE) array in the neural network engine exploits both input and weight sparsity to lower the processing latency by 95%. By using the proposed mixed-precision multiplier in the PE array, the area is reduced by 27% compared with the PE array with the full precision. In the beam search engine, the proposed approximate top-k selection architecture exhibits 16× fewer comparators. The neural signal processor achieves speech decoding with a phone error rate of 16.6% and a word error rate of 23.5%. Fabricated in 40-nm CMOS, the chip achieves the maximum communication rate of 200 words/min, which is 16.7-to-42.6× faster than the state-of-the-art designs. This work is able to decode up to 125,000 words, which is not achievable by prior works that can only decode up to 31 characters.