The new transistor design shows improved subthreshold swing near the Boltzmann constant in 2D materials, suggesting better performance for efficient logic systems.
Abstract 2D materials have shown great potential for next‐generation low‐power transistors due to their excellent electrostatic control and high mobility. However, achieving subthreshold swing approaching the theoretical limit of the Boltzmann constant remains a challenge, primarily due to poor contact quality and limited gate‐channel coupling in these thin materials. Here, a novel WSe 2 ‐based transistor architecture is demonstrated that combines capacitive amplification via a Charge Inversion Layer and contact engineering through a Polarity Gate. The capacitive amplification is enabled by a geometrically asymmetric floating gate structure, where a larger gate area beneath the Mirror Gate induces real‐time charge redistribution, thereby amplifying the gate control over the channel and approaching the Boltzmann limit (≈60 mV dec −1 ). In parallel, a tunable PG is introduced to modulate the injection barrier at the source/drain interface, achieving dynamic control over carrier type and enabling both n‐type and p‐type operation within the same device. Leveraging this reconfigurable platform, a high‐performance CMOS amplifier is further constructed that exhibits a noise margin of 0.97 and a voltage gain of 213 under a supply voltage of 1 V, surpassing previously reported 2D‐material‐based CMOS circuits. The approach opens up new avenues for steep‐slope and energy‐efficient logic systems based on 2D semiconductors.
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Zong et al. (2025) studied this question.
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