What does this research mean for the field?

The proposed 500 MS/s 12b Pipe-SAR ADC achieves 63.4 dB SNDR and 81.0 dB SFDR while consuming only 6.64 mW. Novelty: ClaimNovelty.NOVEL_FINDING. Consensus alignment: ConsensusAlignment.NEUTRAL.

What question did this study set out to answer?

The aim is to present an efficient and linear 12-bit SAR ADC design using advanced amplifier techniques.

March 7, 2026

3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension

Key Points

The aim is to present an efficient and linear 12-bit SAR ADC design using advanced amplifier techniques.
Developed a 28 nm CMOS SAR ADC operating at 500 MS/s.
Utilized a triple-cascode floating residue amplifier with virtual supply extension.
Incorporated on-chip digital calibrations for performance enhancement.
Achieved a signal-to-noise distortion ratio (SNDR) of 63.4 dB.
Attained a spurious-free dynamic range (SFDR) of 81.0 dB at 240 MHz input.
Consumed 6.64 mW of power and occupied a small area of 0.011 mm².

Abstract

This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm2.

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3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension

Key Points

Abstract

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