Demonstrates an ADC design achieving high efficiency and linearity in CMOS technology, suggesting improved performance in analog-to-digital conversion.
This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm2.
No takes yet. Share an insight, caveat, or question.
Rocco et al. (2026) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: