PMA: A High-performance and Low-overhead Parallel Memory Architecture Utilizing Three-dimensional Adaptive Memory Partitioning and Task-driven Scheduling Method for MCMD-based CGRA

The multiple configuration and multiple data-based (MCMD-based) coarse-grained reconfigurable architectures (CGRAs) are employed as popular domain-specific accelerators due to their efficiency and flexibility. However, the existing MCMD-based CGRAs suffer from low hardware utilization and processing performance of dependent tasks due to the limitations of the memory architecture. In this paper, a parallel memory architecture (denoted as PMA) for MCMD-based CGRAs is introduced, which exploits the three-dimensional adaptive memory partitioning method and task-driven scheduling scheme to improve access performance and reduce hardware overhead of CGRAs. The memory access characteristics are analyzed to determine the memory requirements of MCMD-based CGRAs. Then, a three-dimensional memory partitioning method is proposed, which combines dynamic input/output memory partitioning and static shared memory partitioning to improve memory access performance, storage utilization, and throughput of CGRAs. Moreover, a task-driven scheduling scheme is proposed using priority-based task assignment, timeslot matching, and release methods to schedule the data with efficient memory access and non-conflict pipelining. Finally, an overall architecture of PMA is introduced, and the PMA is designed to validate the efficacy of the proposed approach. Experimental results show that PMA reduces 88.26% access time, lowers 40.3% area overhead, and decreases 48.4% power consumption compared to the existing solutions.