Influencing Factors on the Dynamic VSD Behaviour of Different SiC-MOSFET Technologies used for Temperature Read-Out via VSD(T)-Method during the Power Cycling Test at Different Operating Modes

This paper will investigate influencing factors (gate voltage, switch on time etc.) on the dynamic behaviour of the source-drain voltage characteristic (V SD ) of SiC-MOSFETs. V SD is a critical parameter needed for temperature read-out during the power cycling or other reliability test via the V SD (T) method. 1200 V SiC MOSFETs from ten different manufacturers as well as chip generations with approximately same R DSON of 80 mΩ were used in this work. If the off-gate voltage is not sufficiently negative during temperature read-out, a “run-in” behaviour of the forward voltage of the body diode up to a static value occurs for every manufacturer. This should be avoided when determining the temperature of the chip. Otherwise, large errors in temperature detection are likely and possible gate under- and overshoots due to high parasitic gate loops of a power cycling test benches have stronger impact on the transient response of the V SD . Therefore, a sufficiently negative gate voltage should be applied to close the n-channel completely – in some cases even below the allowed datasheet value. Further, it has been confirmed that some manufacturers still face a transient V SD response, although the gate voltage is already very negative, which could make the temperature read-out quite complicated. Furthermore, a small load current (∼1 A for example) has no influence depending on the test mode (MOSFET/3rd Quadrant) on the V SD -response. • Chip technology (SiO 2 /SiC interface defect rate, …) + power cycling test setup (e.g. L G , R G,off , …) defines dynamic V SD behaviour • If the n-channel is completely closed the V SD -value for the planar and asymmetric trench structure is directly stable • For the newer double trench structures further longer lasting dynamic V SD effects were found, although the n-channel is closed • Run gate pulse pattern w/o small load current (∼1A) to detect any temperature readout errors; Compare T C and T vj before start