The growing demand for compact, robust, and energy-efficient power electronic systems has driven intensive research in gallium nitride (GaN) transistor technology over the past two decades. While GaN devices offer superior material properties for high-power and high-performance applications, their widespread adoption in power switching applications has been hindered by reliability concerns, operational mode limitations, and challenges in achieving reliable high-voltage capability. This thesis investigates strategies to enhance GaN device performance, focusing on improved voltage handling capability, reliable enhancement-mode operation, and mitigation of trap-assisted degradation to reduce on-resistance in both lateral and vertical device architectures. A combined approach of experimental characterization and TCAD-based device simulation was employed in this project. Experimentally, the role of channel and nucleation layer thicknesses in buffer-free AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide substrates were analysed. Wafer 2, featuring a thicker GaN channel, delivered the highest drain current density but suffered from increased off-state drain leakage and pronounced dynamic threshold instability at high bias. In contrast, Wafer 3, incorporating a thicker AlN nucleation layer, achieved a more balanced performance with moderate current enhancement, reduced gate leakage, superior breakdown voltage, and improved dynamic stability. In parallel, a novel vertical GaN field-effect transistor was proposed and studied through rigorous TCAD simulations to achieve enhanced electrostatic control and improved breakdown performance. The device incorporates a vertical fin channel fully surrounded by a conformal gate, enabling efficient carrier confinement and transport. Simulation results demonstrate a breakdown voltage of ~1430 V, a threshold voltage of ~1.3 V, and improved forward conduction current, compared to conventional vertical GaN FinFETs with ~840 V breakdown and ~1.0 V threshold voltage. Moreover, the proposed architecture offers a simplified fabrication process compared to the conventional Vertical GaN FinFET. Overall, the findings of this thesis provide valuable insights into design and engineering strategies for both lateral and vertical GaN devices, advancing their potential for nextgeneration, energy-efficient, and high-performance power electronics.
Sahalu Hassan (Thu,) studied this question.