High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform

This is the authors' abstract. We don't add key points for this paper.

The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with <tex-math notation="LaTeX">LG = 2~μ </tex-math> m achieves a large maximum current ( <tex-math notation="LaTeX">Iₘₐₓ) </tex-math> exceeding −20 mA/mm. The InGaN/GaN p-FET obtains a low <tex-math notation="LaTeX">RON </tex-math> of 0.64 k <tex-math notation="LaTeX">Ω · </tex-math> mm and a high <tex-math notation="LaTeX">ION </tex-math>/ <tex-math notation="LaTeX">IOFF </tex-math> ratio exceeding <tex-math notation="LaTeX">10^7 </tex-math>. The device presents E-mode operation with a threshold voltage ( <tex-math notation="LaTeX">VTH) </tex-math> of −1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.