Development of Enhancement-Mode GaN p-FET With Post-Etch Wet Treatment on p-GaN Gate HEMT Epi-Wafer

Developing E-mode p-channel field-effect transistors (p-FETs) on the standard p-GaN gate HEMT epi-wafer is highly motivated to facilitate the realization of gallium nitride (GaN) complementary logic (CL) circuits and power-integrated circuits (PICs). The gate etching process is commonly employed in the fabrication of E-mode GaN p-FETs. However, due to gate etching-induced damage, the performance of E-mode GaN p-FETs often fails to meet expectations. To address the above issue, a post-etch wet treatment technique was developed in this work to enhance the performance of E-mode GaN p-FETs. The fabricated GaN p-FET with <tex-math notation="LaTeX">LG </tex-math> = 2 <tex-math notation="LaTeX">μ m </tex-math> exhibits an E-mode operation with <tex-math notation="LaTeX">Vₜₕ </tex-math> = −2.9 V. The p-FET with post-etch wet treatment exhibits a current density of 5.4 mA/mm. Compared to the p-FET without wet treatment (1.9 mA/mm), the current density has increased by more than double. Atomic force microscopy (AFM) was utilized to characterize the surface morphology and validate the effectiveness of post-etch wet treatment. To suppress the leakage current, multienergy fluorine ion implantation was implemented for planar isolation of GaN p-FETs, high <tex-math notation="LaTeX">ION/IOFF </tex-math> with over <tex-math notation="LaTeX">6× 10^5 </tex-math> was obtained.