Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( <tex-math notation="LaTeX">VDD </tex-math> and <tex-math notation="LaTeX">VDDQ </tex-math> ). The proposed calibration scheme improves system signal integrity by maintaining the targeted output level ( <tex-math notation="LaTeX">VOH </tex-math> ) in dynamic voltage–frequency scaling (DVFS) function, where <tex-math notation="LaTeX">VDD </tex-math> and <tex-math notation="LaTeX">VDDQ </tex-math> can be independently controlled to save system power. A two-step conversion algorithm alleviates the increase in calibration time, which is caused by an additional on-die termination (ODT) calibration for command/address (CA). The offset of a dynamic comparator in a ZQ calibration engine is averaged by a fraction-referred input switching-then-averaging (FISA) scheme which minimizes the effect of kickback noise. A code-referred periodic ZQ update (CPZU) scheme tracks the voltage and temperature variation during the background mode while minimizing the chance of malfunction by interference of both DRAM internal noise and external power noise. By applying the DVFS function based on the device usage by the user scenario in this design ( <tex-math notation="LaTeX">VDD =1.1 </tex-math> V and <tex-math notation="LaTeX">VDDQ = 0.95 </tex-math> V) at 1.6 Gbps, the read and the write operating power consumption can be saved by 17.7% and 18.2%, respectively, without a dynamic drop in performance. Therefore, the proposed dual-loop two-step ZQ calibration design improves the overall DRAM power efficiency based on the existing LPDDR4 SDRAM architecture without circuit overhead.