Path Delay Faults Through Transition Faults with High Functional Switching Activities

Chip aging results in defects that are initially likely to appear as small delay defects. Path delay faults are used for detecting small delay defects. Because of the number of paths, path selection procedures are used for identifying a subset of path delay faults that are important to detect. A recent path selection procedure addresses small delay defects that are likely to occur because of chip aging. The procedure identifies a set of functionally possible path delay faults, from which it selects a subset based on an aging aware metric. This article studies this problem when the requirement for the path delay faults to be functionally possible is removed. The problem becomes that of selecting path delay faults through the largest numbers of transition faults with the highest susceptibilities to aging, and performing test generation for the selected path delay faults. Experimental results of path selection and test generation for benchmark circuits demonstrate the effectiveness of the procedures, and the differences from the case where the path delay faults are required to be functionally possible.