PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
January 1, 1998IEEE Journal of Solid-State Circuits297 citations

A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output

View Full Paper
SDS. DeckerDMDaniel McGrathKBK. Brehmer

Key Points

Key points are not available for this paper at this time.

Abstract

A stepped reset-gate voltage technique is applied to a CMOS active pixel sensor array to increase dynamic range by 26 dB. A frame rate of 390 frames/s is achieved using column-parallel output circuits. Switched-capacitor correlated double-sampling circuits reduce fixed-pattern noise to 4.0 mV (dark). Cyclic analog-to-digital converters achieve approximately 9-b accuracy. At 30 frames/s, random noise is 0.56 mV (dark), optical dynamic range is 96 dB, and power is 52 mW.

Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Decker et al. (1998) studied this question.

synapsesocial.com/papers/6a10b25069378e7f0d9f51b9https://doi.org/10.1109/4.735551
Ask AI
Helpful
Bookmark
Share
View Full Paper