2-D FET Modeling: Why Incorporating the Gate- and Drain-Dependent Source Tunneling Barriers Matter

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This paper presents the modeling of a two-dimensional (2-D) field-effect transistor (FET). By considering two tunneling regions at the source and showing how these regions vary with the gate and drain voltages, a compact model that captures even the non-linear dependence of the drain current at low drain voltages observed in fabricated devices is developed. The proposed model reproduces the results from TCAD simulations and published experimental data with close agreement. This highlights the importance of incorporating the gate- and drain-dependent source tunneling barriers in modeling 2-D FETs.