Key result
TSPC-based CMOS digital frequency divider achieves stable 48.89 MHz operation for low-power biomedical monitoring.
Why the study?
Existing frequency dividers are unsuitable for biomedical monitoring systems requiring low-power frequency synthesis due to high power consumption, increased phase noise, large area requirements, and integration problems.
The proposed TSPC-based CMOS digital frequency divider achieves precise frequency scaling with low power consumption, making it suitable for IoT-driven biomedical monitoring devices.
May enable low-power ADPLL integration in biomedical sensors; leaves open clinical validation for cardiovascular monitoring.
An efficient Digital Phase-Locked Loop (ADPLL) architecture is required for biomedical monitoring systems that depend on low-power frequency synthesis. However, frequency dividers are unsuitable for efficient biomedical applications due to high power consumption, increased phase noise, large area requirements, and integration problems. This research proposes a low-power, compact digital frequency divider for All Digital Phase Locked Loop (ADPLL) RF transceivers, aiming to enhance frequency division accuracy while minimizing power consumption and hardware complexity for biomedical monitoring applications. The proposed digital frequency divider uses TSPC-based CMOS logic to overcome the limitations of conventional frequency dividers, including area, power dissipation, phase noise, and integration issues. This design dynamically switches between divide-by- 2 and divide-by3 modes, effectively achieving a divide-by- 9 operation by using TSPC-based CMOS design, enhancing precise frequency scaling with low power consumption. Implemented using Verilog HDL and validated through simulation achieves stable operation with a divided output clock of 48.89 MHz, derived from DCO output clock of 450 MHz and a 50 MHz reference frequency, ensuring smooth ADPLL integration for energyefficient biomedical monitoring. The ability to scale and the design make it perfect for medical application driven by the Internet of Things and biomedical devices. The future research will be focused on the further optimization of power and the improvement of adaptability for advanced biomedical signal processing.
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Khaliq et al. (2025) studied this question. TSPC-based CMOS digital frequency divider vs. conventional frequency dividers was evaluated on divided output clock frequency. A proposed TSPC-based CMOS digital frequency divider achieved stable operation with a divided output clock of 48.89 MHz, enabling low-power ADPLL integration for biomedical monitoring.
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