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This research aims to develop a low-power digital phase frequency detector to enhance phase-frequency acquisition in ADPLLs used in smart farming.

September 7, 2024

Design of Digital Phase Frequency Detector in ADPLL RF Transceiver

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This research aims to develop a low-power digital phase frequency detector to enhance phase-frequency acquisition in ADPLLs used in smart farming.
Developed a Verilog HDL-optimized digital PFD for ultra-low power applications.
Conducted simulations to evaluate response time and power consumption.
Analyzed phase error detection and correction metrics.
Achieved a duty cycle of 34.2% with no frequency difference.
Obtained a time difference of 0.05 ns, indicating swift phase error management.
Demonstrated fast response time and minimal dead zone impact for efficient phase locking.

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Randomized trial evaluates a digital phase frequency detector's performance in SFMS, indicating energy efficiency benefits.

Khaliq et al. (2024) studied this question.

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