Source and Drain Parasitic Resistances of Amorphous Silicon Transistors: Comparison between Top Nitride and Bottom Nitride Configurations

The source and drain parasitic resistances of amorphous silicon based thin film transistors (aSi:H TFT) are investigated using a very simple TFT model including a parameter extraction method. We show that this method provides an accurate measurement of these resistances and clearly explains their influence on the apparent field effect mobility µ a of the TFTs. We compare the parasitic resistances of TFTs for the top nitride (TN) and bottom nitride (BN) configurations and we show that the usual different performances observed on the two configurations can be mainly attributed to the differences in the parasitic resistances.