A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture

A high-speed and low-voltage associative co-processor with exact Hamming or Manhattan distance estimation is presented. The word-parallel and hierarchical search architecture is achieved using a logic-in-memory digital implementation. In the bit-serial search architecture, it is important to shorten the search cycle time since the total search time generally increases in proportion to the bit length. The present hierarchical architecture achieves a high-speed operation with a large input number. Furthermore, it provides a result for the data close to the input with a fewer number of clocks. Therefore, it reduces the number of clocks required for nearest-match detection in practical use. The circuit implementation allows unlimited database capacity and achieves a low-voltage operation under 1.0 V for system-on-a-chip applications. The capacity scalability makes it easy to compute a function of Manhattan distance estimation using thermometer encoding. A 64-bit 32-word associative co-processor has been designed using a one-poly-Si five-metal 0.18-/spl mu/m CMOS process and has been successfully tested. The measurement results show that the operation achieves a speed of 411.5 MHz at a supply voltage of 1.8 V. The worst-case search time is 158.0 ns for a 64-bit 32-word database. In a low-voltage operation, the operation speed achieves 40.0 MHz at a supply voltage of 0.75 V.