This work investigates a hardware-aware, circuit-level emulation of BB84-like circuit primitives on noisy intermediate-scale quantum (NISQ) processors. The motivation is to evaluate whether BB84-like basis sifting and intercept–resend-induced QBER behavior remain observable when selected BB84 operations are mapped to parallel single-qubit circuits on gate-based devices. The proposed mapping represents Alice’s preparation, optional Eve intercept–resend emulation, and Bob’s measurement as processor-internal circuit layers; it is therefore an on-chip emulation and not an end-to-end optical QKD implementation. Experiments combine real IBM superconducting processors with Qiskit, Cirq, and Azure/Q# simulator-based or noise-modeled evaluations. Baseline QBER was first calibrated for each backend, and intercept–resend experiments then produced a clear QBER separation from the no-eavesdropper condition. The observed sifted-bit utilization was close to the expected 50% BB84 basis-matching reference, while the constant-depth circuit structure supported scalable raw/sifted-bit generation before any classical post-processing. These observations are treated as implementation-level consistency checks and backend-dependent experimental metrics, rather than as new BB84 protocol-level results. Finite-shot uncertainty, calibration drift, and backend-specific noise are treated as limitations of the proposed QBER-based evaluation rule rather than as deployment-level security guarantees. Because the study does not implement a physical quantum channel, authenticated classical communication, error correction, privacy amplification, finite-key security analysis, or general QKD attack models, the reported metrics should be interpreted as raw/sifted-bit experimental metrics and QBER-based disturbance evaluation for BB84-like NISQ emulation, not as secure key rates, secure throughput, or practical QKD deployment results.
Chang et al. (Mon,) studied this question.